1. Field of the Invention
This invention relates to the field of integrated circuit (I.C.) fabrication methods, and particularly to methods of protecting features formed with thin film processes.
2. Description of the Related Art
"Thin film" processing is used to create structures or features on an integrated circuit wafer from a thin layer of material that has been deposited on top of an oxide layer formed on a substrate. Resistors, for example, are commonly fabricated using thin film techniques.
Present thin film processing methods, discussed, for example, in A. Grebene, Bipolar and MOS Analoa Circuit Design, John Wiley & Sons (1984) pp. 22-26, possess several inherent characteristics that can adversely affect the performance of the resistors they are used to create. Thin film resistors, particularly those made from silicon chromium carbide (SiCrC), are fabricated per the following "back-end" process steps, i.e., steps performed after an I.C.'s active devices have been formed:
1. Contact Mask. With an oxide layer formed atop a silicon substrate, a contact mask step opens holes in the oxide where metal is to make contact to the silicon, for connection to the diffused terminals of a transistor, for example.
2. Sputter Platinum/sinter/strip. This step forms platinum silicide (PtSi.sub.2) wells at the bottom of the contact openings made in step 1. First, platinum is sputtered on the wafers. Next, a sinter is performed in which the platinum is annealed at about 500.degree. C. for about 30 minutes in dry nitrogen (N.sub.2). During anneal, the platinum reacts with the silicon substrate and forms the PtSi.sub.2 wells. After anneal, unreacted platinum is stripped, typically with a solution containing hydrochloric acid (HCl) and nitric acid (HNO.sub.3).
3. Sputter Thin Film (TF). Here, the actual resistor material, typically SiCrC, is sputtered on the wafer.
4. Sputter Titanium Tungsten (TiW) and Aluminum Silicon Copper (AlSiCu). TiW is sputtered first, to provide a thin (.about.900 .ANG.) barrier layer under the metal which helps with electromigration and current density, as well as improving the contacts to the TF resistor material. AlSiCu is then sputtered on top of the TiW; it is the primary metal and carries the resistor current.
5. Metal 1 Mask. This step dry etches AlSiCu, TiW and SiCrC according to the metal 1 mask pattern to define the chip's metal traces and the resistor boundaries.
6. Thin Film Open Mask (TFOP). AlSiCu and TiW over the resistors are wet etched with hydrogen peroxide. This step removes material all the way down to the resistor's surface. A wet etch must be used because a dry etch would cause severe damage to the thin film resistor defined in step 5.
This process suffers from a number of problems, some of which arise due to the necessity of using a wet etchant such as hydrogen peroxide to etch the excess TiW in step 6. Since it is a wet etchant, it will undercut the TiW which is intended to remain as a barrier material for the resistor contacts. The degree of undercutting is very difficult to control in a manufacturing environment, so that a resistor's length--which is defined by the TiW contact areas at its two ends--becomes somewhat unpredictable. The undercutting produces non-uniformity between resistors that impacts resistor accuracy and matching, and can cause ragged edges which further complicate matching. Also, etching TiW in smaller "cuts", i.e., small open areas in the TFOP masking layer, can be difficult. Particularly for wafers with a high degree of surface tension, cuts which do not open up from a wet etch are common. This leaves some residual TiW in the small cuts after the TFOP etch, which can result in resistor matching problems. These wet etch-induced problems also tend to increase the minimum spacing that can be tolerated between metal traces.
Another problem arises by performing the thin film sputter step after the PtSi.sub.2 wells are created. Exposing PtSi.sub.2 to the thin film sputter will cause it to be partially etched away and thinned down, particularly in the contact area's corners where there is a higher electric field. Because the PtSi.sub.2 improves contact to the silicon, this sequence of steps can degrade the quality of the connections to the chip's active devices.